/******************************************************************************
*
* MODULE:    Receptor_Asc.v
* DEVICE:     
* PROJECT:   Tarea 1 Diseño Electronico Digital
* AUTHOR:    Ricardo Dávila Castro   
* DATE:      2010 14:37:48
*
* ABSTRACT:  Receptor Serial Ascincrono Ejercicio Dos
*            
*******************************************************************************/

`ifndef 	RECEPTOR_ASC
`define    RECEPTOR_ASC

module Receptor_Asc (
input clk,
input serial_in,
input en,
output [8:0]data_out,
output valid_data ,
output reg parity_error
);

reg [8:0]data;
reg par=0;
reg stop=0;
reg start;
reg [3:0]cont;


always @ (posedge en)
	begin
	 start <= serial_in; //bit control
	end

always @ (posedge clk)
begin
	if (!start) 
	begin 
		cont <= 4'b0000; 
		repeat (9) 
		begin
				@(posedge clk);
				data[cont] <= serial_in; 
				cont<=cont+1;
		end
		
		stop <= serial_in; //una vez que se guardan los bits y el bit paridad se graba el bit paro
		//par = ^data;
	end
end

always @ *
begin
		 par = ^data;//calculo paridad
		if (par) 
		parity_error = 1'b1; 
		else
		parity_error = 1'b0; 
end

assign data_out = data;
assign valid_data = (!par && stop) ? 'b1: 'b0;

endmodule 
`endif
